TP 12.5: A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL Architecture

The growing importance of wireless media for voice and data communications is driving a need for higher integration in personal communications transceivers in order to achieve lower cost, smaller form factor, and lower power dissipation [1]. One approach to this problem is to integrate the RF functionality in low-cost CMOS technology together with the baseband transceiver functions. This in turn requires integration of the frequency synthesizer with enough isolation from supply noise to allow the synthesizer to coexist with other on-chip transceiver circuitry and still meet the phase noise performance requirements of the application. This paper describes a differential synthesizer for block-down-convert receivers that achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture and a wide-bandwidth PLL.